// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module vin_crop 
(
    input  wire I_pclk,
    input  wire I_new_frame,
    input  wire I_de,
    input  wire [ 23: 0] I_data,
    output reg  O_de,
    output reg  [ 23: 0] O_data,
    input  wire [ 11: 0] I_reg_row_offset,
    input  wire [ 11: 0] I_reg_col_offset,
    input  wire [ 11: 0] I_reg_vin_max_width,
    input  wire [ 11: 0] I_reg_vin_max_height

);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  [ 12: 0] col_cnt;
reg  [ 12: 0] row_cnt;
reg  de_dly;
reg  de;
reg  [ 23: 0] data;

/******************************************************************************
                                <module body>
******************************************************************************/
always @(posedge I_pclk)
    de_dly <= I_de;

always @(posedge I_pclk)
    if (!I_de)
        col_cnt <= 'd0;
    else
        col_cnt <= col_cnt + 1'b1;

always @(posedge I_pclk)
    if (I_new_frame)
        row_cnt <= 'd0;
    else if (!I_de && de_dly)
        row_cnt <= row_cnt + 1'b1;

always @(posedge I_pclk)
    if (col_cnt >= I_reg_col_offset && row_cnt >= I_reg_row_offset 
        && col_cnt < I_reg_col_offset + I_reg_vin_max_width
        && row_cnt < I_reg_row_offset + I_reg_vin_max_height)
        begin
        O_de <= I_de;
        O_data <= I_data;
        end
    else
        begin
        O_de <= 1'b0;
        O_data <= 24'd0;
        end

endmodule
`default_nettype wire

